Job Description

Design Verification Engineer, DFT/DFD

Job location: United States (Remote)

In this role, you will verify Design-for-Test (DFT) and Design-for-Debug (DFD) logic-including JTAG, iJTAG, and internal scan architectures-ensuring robust manufacturability and post-silicon debuggability. You will work closely with DFT architects, RTL designers, and DV teams to develop and execute comprehensive verification plans using industry-standard tools and methodologies.

This is a fixed-term contract role and the candidates can be based in the US or Canada, and we are open to remote work.

Key Responsibilities:

• Define and execute verification plans for DFT/DFD features such as boundary scan, scan chains, and debug logic.
• Develop UVM-based or directed tests to validate IEEE 1149.x (JTAG), 1500 (iJTAG), and 1687 (IJTAG) compliant implementations.
• Verify integration and functionality of ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) content for instrument and test control.
• Simulate and debug DFT/DFD RTL and gate-level designs using industry-standard simulators.
• Collaborate with DFT architecture and implementation teams to ensure functional correctness, performance, and alignment with manufacturability goals.
• Drive coverage closure, including code coverage and functional coverage, across all DFT/DFD blocks.
• Work with post-silicon validation and ATE teams to ensure test vector portability and alignment between simulation and silicon.

Experience & Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 7-8 years hands-on experience with focus on DFT/DFD.
• Proven experience in design verification for DFT/DFD architectures in complex SoC environments.
• Hands-on experience with IEEE JTAG-related standards: 1149.1, 1500, and 1687.
• Proficiency in writing and debugging ICL and PDL files for test generation and instrumentation control.
• Experience using Siemens Tessent tool suite for scan insertion, ATPG, IJTAG, and pattern generation.
• Solid understanding of RTL verification flows and simulation methodologies.
• Proficiency in Verilog/SystemVerilog and scripting (Python, Perl, TCL).
• Strong analytical and debugging skills with attention to detail and documentation.
• Experience with UVM-based testbench environments for DFT/DFD verification. (preferred)
• Familiarity with scan compression, LBIST/MBIST, and test access architectures. (preferred)
• Exposure to gate-level simulations and post-silicon test bring-up workflows. (preferred)
• Strong collaboration skills with ability to work across architecture, design, and ATE teams. (preferred)
• Knowledge of scan diagnosis and failure analysis workflows is a plus. (preferred)

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